Construct 2 to 4 decoder with truth table and logic diagram

Just as Multiplexer, Decoder is also a Combinational circuit  which transforms given inputs to maximum number of outputs(maximum outputs equal to 2n and n are given inputs ).
A block diagram of decoder consists input lines, one or more enable inputs and maximum number of output lines.
To construct a decoder, we require to know the number of all possible output lines that totally depends on the given input.
So, if  n represents given input lines then possible output lines would be 2n .
Decoder with two inputs would give 4 outputs (n=2,2that is 4).

Step 1. Now we know possible outputs for 2 inputs, so construct 2 to 4 decoder , having 2 input lines, a enable input and 4 output lines. In the below diagram, given input represented as Iand I, all possible outputs named as  O0, O1, O2, & Oand a E were represented by Enable input.

With Enable input

2 2BTO 2B1 2Bdecoder

 

Without Enable input

2 2BTO 2B1 2Bdecoder 1

Step 2. Now, it turns to construct the truth table for 2 to 4 decoder. E input can be considered as the control input. Mean to say, If E equals to 0 then the decoder would be considered as disabled regardless of what inputs are,  If E equals to 1 then the decoder would work as per inputs.

Truth table without E input

 

InputsOutputs
I1I0O3O2O1O0
000001
010010
100100
111000

As per the above table, I0 would give Oand O3 and I1 would give O1 and O3.
We can represent the following output as:

O= I0‘.I1
 O= I0.I1

 O= I0‘.I1
 O3 = I0.I1


Truth table with E input

InputsOutputs
EI1I0O3O2O1O0
00000
1000001
1010010
1100100
1111000

Decoder with E

2 2Bto 2Bdecoder 2Bdiagram 2Bwith 2BE

 

Explanation:

In above diagram, there were two input lines along with their complements using Inverters. Each and every AND gate were holding three inputs from E, Iand Iand producing 4 outputs.

Decoder Without E

2 2Bto 2Bdecoder 2Bdiagram

Explanation:

In above diagram, there were two input lines with their respective complements using Inverters. Each and every AND gate were holding two inputs from Iand Iand producing 4 outputs.

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