Construct 3 to 8 decoder with truth table and logic gates

Share

Decoder is also a Combinational circuit which transforms given inputs to a maximum number of outputs (maximum outputs equal to 2n and n are given inputs ).

In other words, a decoder can be defined as a logic circuit that receives binary input and produces output corresponding to that very binary input.

A block diagram of decoder consists of n input lines, one or more enable inputs and 2n maximum number of output lines.

To construct a decoder, we require to know the number of all possible output lines that totally depends on the given input.

So, if n represents given input lines then possible output lines would be 2n.
Decoder with three inputs would give 8 outputs (n=2,2that is 8).

In this article, we’ll be going to design 3 to 8 decoder step by step.

Here are the steps to Construct 3 to 8 Decoder

Step 1. Now we know possible outputs for 3 inputs, so construct 3 to 8 decoder, having 3 input lines, a enable input and 8 output lines.

In the below diagram, given input represented as I2Iand I, all possible outputs named as  O0, O1, O2,O3O4, O5,O6 Oand a E were represented by Enable input.

With Enable input

Without Enable input




Step 2. Now, it turns to construct the truth table for 3 to 8 decoder. E input can be considered as a control input.

Mean to say, If E equals to 0 then the decoder would be considered as disabled regardless of what inputs are,  If E equals to 1 then the decoder would work as per inputs.

Truth table without E input

InputsOutputs
I2I1I0O7O6O5O4O3O2O1O0
00000000001
00100000010
01000000100
01100001000
10000010000
10100100000
11001000000
11110000000

We can represent the following output as:

O= I0‘.I1.I2
O= I0.I1.I2

O2 = I0‘.I1.I2
O3 = I0.I1.I2
O4 = I0.I1.I2
O5 = I0.I1.I2
O6 = I0.I1.I2
O7 = I0.I1.I2


Truth table with E input

Inputs
Outputs
EI2I1I0O7O6O5O4O3O2O1O0
0---00000000
100000000001
100100000010
101000000100
101100001000
110000010000
110100100000
111001000000
111110000000

Step 3. With the help of the above expressions derived from the table, the circuit of a 3 to 8 decoder can be implemented.

Decoder Without E

Explanation:

In the above diagram, there were three input lines with their respective complements using Inverters. Each and every AND gate were holding three inputs from I1Iand Iand producing 8 outputs.

Decoder with E

 

Explanation:

In above diagram, there were three input lines along with their complements using Inverters. Each and every AND gate were holding four inputs from E, I1Iand Iand producing 8 outputs.

This post was last modified on April 7, 2021

Sandeep Verma

Published by
Sandeep Verma
Tags: 3 to 8 decoder Computer organisation Construct 3 to 8 decoder with truth table and logic gates decoder Digital Electronic logic gates Multiplexer