Design a 2 bit Synchronous down counter using T Flip flop?

These are the following steps to design a 2 bit synchronous down counter using T Flip flop:

Step 1: To design synchronous down counter, we just require to change the order of present state and next state, just put 0 where is 1 in synchronous up counter. In other words, start from 11 (3) to 00 (0)

Step 2: After that, we need to construct a state table with excitation table.
Note: To construct excitation table from state table you should know the excitation table of respective flip flop, in this case, it is T flip flop. So check the excitation table forT flip flop Which is:

T Flip Flop Excitation Table

So, the above table is the excitation table for T Flip Flop.

State Table with  excitation  table

Above the table is created as per follow :

When Q₂ =1 which is present state and Q₂‘=1 which is next state then T₂ become 0 [As per excitation table, have a look ]
Similarly, if Q₂ is 1and Q₂‘ is 0 then T_{2 becomes} 1.
In a similar way, it goes on.

Step 3: After making the excitation table the next thing to do is dig out the equation from the boolean algebra or K map for the design of the counter. So For T₁ and T₂ we got 1 and Q₁‘ .

K-Map

For T_{2  Flip flop,}

For T₁ Flip flop,

Step 4: Lastly according to the equation got from K map create the design for 2 bit synchronous down counter.

In above design T₁ is getting high input  and T₂ is getting input from the output of the T₁ which is complement of the output.  A clock is attached to it which is always high in blue color.