Design a 2 bit Synchronous down counter using T Flip flop?

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These are the following steps to design a 2 bit synchronous down counter using T Flip flop:

Step 1: To design synchronous down counter, we just require to change the order of present state and next state, just put 0 where is 1 in synchronous up counter. In other words, start from 11 (3) to 00 (0)

Step 2: After that, we need to construct a state table with excitation table.
Note: To construct excitation table from state table you should know the excitation table of respective flip flop, in this case, it is T flip flop. So check the excitation table forT flip flop Which is:

T Flip Flop Excitation Table

Present stateNext State   T
000
011
101
110

So, the above table is the excitation table for T Flip Flop.


State Table with  excitation  table

 Present State   Next State   Flip Flop
Q2Q1Q'2Q'1T2T1
001111
010001
100111
111001

Above the table is created as per follow :

When Q2 =1 which is present state and Q2‘=1 which is next state then T2 become 0 [As per excitation table, have a look ]
Similarly, if Q2 is 1and Q2‘ is 0 then T2 becomes 1.
In a similar way, it goes on.

Step 3: After making the excitation table the next thing to do is dig out the equation from the boolean algebra or K map for the design of the counter. So For T1 and T2 we got 1 and Q1‘ .

K-Map

For T2  Flip flop,

 

 

 

 

T2= Q1

For TFlip flop,

 

T1=1

Step 4: Lastly according to the equation got from K map create the design for 2 bit synchronous down counter.

In above design T1 is getting high input  and T2 is getting input from the output of the T1 which is complement of the output.  A clock is attached to it which is always high in blue color.

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This post was last modified on March 10, 2024

Sandeep Verma

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Sandeep Verma
Tags: 2 bit Synchronous down counter Computer organisation counter de digital electronics t flip flop