These are the following step to design a 2 bit Synchronous up counter using T Flip flop
Step 1: To design a synchronous up counter, first we need to know what number of flip flops are required. we can find out by considering a number of bits mentioned in the question. So, in this, we required to make 2 bit counter so the number of flip flops required is 2 [2n where n is a number of bits].
Step 2: After that, we need to construct a state table with an excitation table.
Note: To construct an excitation table from the state table you should know the excitation table of the respective flip flop, in this case, it is T flip flop. So check the excitation table forT flip flop Which is:
T Flip Flop Excitation Table
| Present state | Next State | T |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
So, the above table is the excitation table for T Flip Flop.
State Table with excitation table
| Present State | Next State | Flip Flop | |||
|---|---|---|---|---|---|
| Q2 | Q1 | Q'2 | Q'1 | T2 | T1 |
| 0 | 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 | 1 |
Above the table is created as per follow :
When Q2 =0 which is the present state and Q2‘=0 which is the next state then T2 becomes 0 [As per excitation table, have a look ]
Similarly, if Q2 is 0 and Q2‘ is 1 then T2 becomes 1.
In a similar way, it goes on.
Step 3: After making the excitation table the next thing to do is dig out the equation from the boolean algebra or K map for the design of the counter. So For T1 and T2 we got 1 and Q1 .
K-Map
For T2 Flip flop,
For T1 Flip flop,
Step 4: Lastly according to the equation got from K map create the design for 2 bit synchronous up counter.
In the above design, T1 is getting high input and T2 is getting input from the output of the T1 flip flop. A clock is attached to it which is in blue colour.