Computer organisation – Programmerbay https://programmerbay.com A Tech Bay for Tech Savvy Sun, 10 Mar 2024 16:46:31 +0000 en-US hourly 1 https://wordpress.org/?v=6.7.1 https://programmerbay.com/wp-content/uploads/2019/09/cropped-without-transparent-32x32.jpg Computer organisation – Programmerbay https://programmerbay.com 32 32 Design a 2 bit Synchronous down counter using T Flip flop? https://programmerbay.com/design-a-2-bit-synchronous-down-counter-using-t-flip-flop/ https://programmerbay.com/design-a-2-bit-synchronous-down-counter-using-t-flip-flop/#respond Fri, 01 Mar 2024 15:03:00 +0000 http://programmerbay.com/?p=3112

These are the following steps to design a 2 bit synchronous down counter using T Flip flop:

Step 1: To design synchronous down counter, we just require to change the order of present state and next state, just put 0 where is 1 in synchronous up counter. In other words, start from 11 (3) to 00 (0)

Step 2: After that, we need to construct a state table with excitation table.
Note: To construct excitation table from state table you should know the excitation table of respective flip flop, in this case, it is T flip flop. So check the excitation table forT flip flop Which is:

T Flip Flop Excitation Table

Present stateNext State    T
000
011
101
110

So, the above table is the excitation table for T Flip Flop.


State Table with  excitation  table

   Present State    Next State    Flip Flop
Q2Q1Q'2Q'1T2T1
001111
010001
100111
111001

Above the table is created as per follow :

When Q2 =1 which is present state and Q2‘=1 which is next state then T2 become 0 [As per excitation table, have a look ]
Similarly, if Q2 is 1and Q2‘ is 0 then T2 becomes 1.
In a similar way, it goes on.

Step 3: After making the excitation table the next thing to do is dig out the equation from the boolean algebra or K map for the design of the counter. So For T1 and T2 we got 1 and Q1‘ .

K-Map

 

For T2  Flip flop,

 

2 2BBIT 2BDown

 

 

 

T2= Q1

For TFlip flop,

Q2

 

T1=1

Step 4: Lastly according to the equation got from K map create the design for 2 bit synchronous down counter.

2 2BBIT 2BDown 2Bdesign

In above design T1 is getting high input  and T2 is getting input from the output of the T1 which is complement of the output.  A clock is attached to it which is always high in blue color.

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Design a 2 bit Synchronous up counter using T Flip flop?

 

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Design 2 bit Synchronous up counter using T Flip flop? https://programmerbay.com/design-a-2-bit-synchronous-up-counter-using-t-flip-flop/ https://programmerbay.com/design-a-2-bit-synchronous-up-counter-using-t-flip-flop/#respond Thu, 29 Feb 2024 16:35:00 +0000 http://programmerbay.com/?p=3115

These are the following step to design a 2 bit Synchronous up counter using T Flip flop

Step 1: To design a synchronous up counter, first we need to know what number of flip flops are required. we can find out by considering a number of bits mentioned in the question. So, in this, we required to make 2 bit counter so the number of flip flops required is 2 [2n where n is a number of bits].

Step 2: After that, we need to construct a state table with an excitation table.

Note: To construct an excitation table from the state table you should know the excitation table of the respective flip flop, in this case, it is T flip flop. So check the excitation table forT flip flop Which is:

T Flip Flop Excitation Table

Present stateNext State    T
000
011
101
110

So, the above table is the excitation table for T Flip Flop.


State Table with  excitation  table

   Present State    Next State    Flip Flop
Q2Q1Q'2Q'1T2T1
000101
011011
101101
110011

Above the table is created as per follow :

When Q2 =0 which is the present state and Q2‘=0 which is the next state then T2 becomes 0 [As per excitation table, have a look ]
Similarly, if Q2 is 0 and Q2‘ is 1 then T2 becomes 1.
In a similar way, it goes on.

Step 3: After making the excitation table the next thing to do is dig out the equation from the boolean algebra or K map for the design of the counter. So For T1 and T2 we got 1 and Q1 .

K-Map

 

For T2  Flip flop,

k 2Bmap1
T2= Q1

For TFlip flop,

k 2Bmap2

 

T1=1

Step 4: Lastly according to the equation got from K map create the design for 2 bit synchronous up counter.

2 bit Synchronous up counter using T Flip flopIn the above design, T1 is getting high input and T2 is getting input from the output of the T1 flip flop.  A clock is attached to it which is in blue colour.

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Design 3 bit synchronous up counter using T Flip flop? https://programmerbay.com/design-a-3-bit-synchronous-up-counter-using-t-flip-flop/ https://programmerbay.com/design-a-3-bit-synchronous-up-counter-using-t-flip-flop/#respond Sun, 25 Feb 2024 16:04:00 +0000 http://programmerbay.com/?p=3114

These are the following steps to Design a 3 bit synchronous up counter using T Flip flop:

Step 1: To design a synchronous up counter, first we need to know what number of flip flops are required. we can find out by considering a number of bits mentioned in the question. So, in this, we required to make 3 bit counter so the number of flip flops required is 3 [2n where n is a number of bits].

Step 2: After that, we need to construct state table with excitation table.
Note: To construct excitation table from state table you should know the excitation table of respective flip flop, in this case, it is T flip flop. So check the excitation table for T flip flop Which is:

T Flip Flop Excitation Table

Present stateNext State    T
000
011
101
110

So, the above table is the excitation table for T Flip Flop.

State Table with  excitation  table

   Present State    Next State    Flip Flop
Q3Q2Q1Q'3Q'2Q'1T3T2T1
000001001
001010011
010011001
011100111
100101001
101110011
110111001
111000111

Above  table is created as per follow :

When Q3 =0 which is present state and Q3‘=0 which is next state then T3 become 0 [As per excitation table, have a look ]
Similarly, if Q3 is 0 and Q3‘ is 1 then T3  become 1.
In similar way it goes on .

Step 3: After making the excitation table the next thing  to do is dig out the equation from the boolean algebra or K map for the design of the counter. So, for T1 , Tand T3 we got 1,  Q1 and Q1.Q2

K-Map

 

For TFlip flop,

 

3biit
T3= Q1.Q2

For T2  Flip flop,

3bit1
T2= Q1

For TFlip flop,

3biit2t

 

T1=1

Step 4: Lastly according to the equation got from K map create the design for 3 bit synchronous up counter.

design 2B3bit

In above design, T1 is getting input 1 and T2 is getting input from the output of the T1 flip flop and lastly, T3 is getting input from the output of T1  and T2 . A clock is attached to it which is in blue colour.

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Difference Between HDLC And PPP Protocol in Tabular Form https://programmerbay.com/difference-between-hdlc-and-ppp-protocol/ https://programmerbay.com/difference-between-hdlc-and-ppp-protocol/#respond Mon, 19 Sep 2022 09:37:16 +0000 https://www.programmerbay.com/?p=2631 In this article, we’ll be discussing HDLC & PPP data link protocols and the differences between them.

HDLC and PPP  protocols are the communication protocol responsible for transmitting information between nodes or points. It deals data in form of frames.

Both HDLC and PPP are the part of data link layer. The major difference between them is, HDLC refers to bit-oriented protocol, whereas, PPP is byte-oriented protocol.

Difference between High-level Data Link Control Protocol and Point-To-Point protocol

HDLCPPP
It stands for High-level Data Link Control protocolIt stands for Point-To-Point protocol
It is a Bit-oriented protocolIt is a Byte-oriented protocol
The HDLC protocol is only used for the synchronous mediaThe PPP protocol is used for both the asynchronous media as well as synchronous media
It is an older protocol as compared to PPP protocol so it does not provide any kind of authenticationIt is the newer protocol as compared to HDLC protocol which means that it does provide the authentication.
In this, the addressing is not dynamic which means that the addressing is purely static.
In this, the addressing is dynamic which makes it quite reliable than HDLC protocol.
As the HDLC protocol is a quite old school which purely signifies that it does not support non-cisco devices at all.The PPP protocol is relatively newer than the HDLC protocol which signifies that it does support the non-cisco devices.
It is more costlier than PPPIt is less costlier than HDLC

High-Level Data Link Control ( HDLC )

HDLC stands for High-level Data Link Control. HDLC is a type of WAN protocol which necessarily performs the encapsulation of data inside the data link layer. This is the type of encapsulation which changes the format of data and information.

Furthermore,it is used to exchange data between nodes. It transmits data in the form of frames over a network.

It allows the use of point to point and multipoint links. It provides two types of transfer modes that is:

  • Normal Response Mode (NRM): In this, station’s configuration is unbalanced. NRM involves a primary station that is capable of sending commands and multiple secondary station that can only response.
    • It can be used as point to point that includes one primary station and a secondary station that communicate with each other.
    • Other is, point to multi-point, it involves one primary station and multiple secondary stations that communicate with one other.

 

  •  Asynchronous Balanced Mode (ABM): In this, station’s configuration is balanced. It involves only point to point communication which means single primary station and a secondary station are the part of communication. The main difference is, every station can send and receive data.

Types of frames in HDLC

It generally supports three types of frames:

  •  Information frames or I frames
  •  Supervisory frames or S frames
  • Unnumbered frames or U frames

Frame format of HDLC

It consists 6 types of fields:

HDLC frame formate

  • Flag: It used to verify beginning and end of a frame. It serves synchronisation pattern for receiver
  • Address: It consists address of the receiving station
  • Control: It is used for error control and flow control
  • Payload :Contains users data
  • FCS: It stands for frame check sequence that is dedicated to error detection

 

Point to Point Protocol ( PPP )

PPP stands for Point-To-Point protocol. PPP is also a type of WAN protocol, which comes up with loads of advancements over the HDLC protocol. PPP protocol does not need any physical addresses or any tangible wires, only the IP address is sufficient.

It defines format of frames, connection establishment, data exchange process, Authentication process and more. However, it doesn’t support flow control, addressing mechanism and efficient error control

Frame format of PPP:

PPP Protocol format

  • Flag: used to verify beginning and end of a frame. It serves synchronisation pattern for receiver
  • Address: It consists address of the receiving station. A constant value is used to set the address field which is 11111111 that resembles broadcast address
  • Control: A constant value is used to set the field which is 11000000 . Since, flow control is not supported and PPP has very limited error control. Tberefore, it is generally not needed
  • Protocol : It decides the data that is going to transmit
  • Payload field :Contains users data
  • FCS: It stands for frame check sequence that is dedicated to error detection

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How to Find Product Of Sums or POS from Truth Table ? https://programmerbay.com/how-to-find-product-of-sums-from-truth-table/ https://programmerbay.com/how-to-find-product-of-sums-from-truth-table/#respond Tue, 10 May 2022 08:56:00 +0000 http://programmerbay.com/?p=3098

Product Of Sum or POS Form

POS stands for Product of Sum and totally opposite to SOP form . When an expression is expressed in a product of binary terms ( A term refers to a set of binary variables, where each binary variable is combined with an operation) called Maxterms than it is said to be Product of Sum.

In other words, An expression consisting only Maxterms is called Product of Sum. For  example, (A+B)(A’+B) is a POS expression.
[other concept Minterms, A.B+A’B’]

POS can be categorized in two forms :

– Canonical or Standard POS form: In this, each and every binary variable must have in each term. For example :- (A+B).(A’+B).

– Minimal POS form: In this, the standard POS expression is reduced up in the minimum possible expression.

product 2Bof 2Bsum

A Question can be asked in three ways:-

1) In the form Truth table
2) In the form of non-canonical Expression
3) In the of form of Boolean function

 For the given table, simplify it in POS expression

Or

Find POS from Truth Table

A B Y
0 0 0 (M0)
0 1 0 (M1)
1 0 1 (M2)
1 1 1 (M3)

 

Points to Remember :

  • Always consider low output (0)
  • In Product of Sum or POS, every term in the expression is refereed to Maxterm
  • A Maxterm is represented as M(Capital M)
  • Consider A’ =1, A=0




Step 1. Since there are 2 variables , so therefore there would be 2n combinations which is 22 =4.
We consider a low output as Maxterm . a Maxterm is denoted as M.
Y= M0+M1
Y = (A+B).(A+B’)                           :- It is in Canonical POS form

In Product of Sum each term is combined with AND operation and within each term, every variable combined with OR operation.

Step 2. Now narrow the founded expression down to minimal Product of Sume or POS form. In this, you should know rules of Boolean expression or K-map

Y= A+BB’                         :-  x+yz = (x+y)(x+z)
Y= A + 0                            :- x.x’ =0
Y= A

OR

Considering, A= 0, A’=1

product 2Bof 2Bsum 2B2 2Bvariable 2B



Y= A

A is your answer.

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Difference Between RISC And CISC Machine in Tabular Form https://programmerbay.com/difference-between-risc-and-cisc-machine/ https://programmerbay.com/difference-between-risc-and-cisc-machine/#respond Sun, 14 Mar 2021 16:35:15 +0000 https://www.programmerbay.com/?p=2622 A processor, or say more precisely CPU (Central Processing Unit ) can be defined as an integrated circuit that is responsible for processing stored instructions. The primary operations of a CPU are:
– Fetch : Receiving instructions from memory
– Decode – Convert it into binary instructions
– Execute – Operation is performed
– Store – Saving output to memory

CISC Vs RISC

It can have two types of CPU architecture, CISC and RISC. Both provides communication between hardware and software.

These CPU architectures are capable of carrying out primary CPU tasks, though, they follow different approaches. The main difference between them is, CISC supports more instruction sets than RISC.

Difference between RISC AND CISC in Tabular Form

BasisRISCCISC
Stands forReduced Instruction Set ComputerComplex Instruction Set Computer
Size of instructionsSmaller and simpler instructionsLarger and Complex instructions
Execution Time1 cycle per instructionMultiple number of cycles per instruction
Emphasis On SoftwareOn hardware
Instruction FormatsFixed (4 bytes)Variable Length (2-6 bytes)
Control UnitHardwired Control UnitMicroprogrammed Control Unit
Data and Instruction CacheSeparateCombined
Example of processorsARM processor and Qualcomm processor are some examplesAMD, VAX and Intel x86 CPUs are some examples
CPU sizeSmallerLarger as they have larger instruction libraries
Addressing ModesFewerMany
ArrayNot SupportedSupported
PipelineEasyHard
Power consumptionLessMore
Referred asMachine OrientedProgrammer Oriented
Register setsHas multiple register setsHas Single register set
Memory unit Doesn't have memory unit Have memory unit

RISC (Reduced Instruction Set Computer)

It stands for Reduced Instruction Set Computer.

It is basically conceptualized on the fact of making hardware simpler and less complex. And this is done by implementation of the Instruction set which reduces the load on processes like loading, storing and evaluating data.

risc

In other words, it has an assembly language that enables each and every task to be split into simpler instructions which are then executed for each clock cycle. Its instructions are efficient but due to simplicity it processes more lines of code.

It focuses on reducing execution time by optimising and simplifying instruction set. It requires only single clock cycle to process results in uniform execution time. However, it reduces efficiency in case of large program size which leads to need of more RAM for storing instruction.

RISC architecture is often used in portable devices such as mobile phones.

CISC (Complex Instruction Set Computer)

It stands for Complex Instruction Set Computer.

It is basically based on complex hardware and all the importance is given to that always. This is done by implementing complex hardware which serves as a single instruction for all the processes like loading, storing and evaluating data.

In other words, It processes larger and more complex assembly instructions each time. One CISC instruction can do the task of multiple RISC instructions.

CISC

It focuses on reducing the number of instructions per program without considering the number of cycles per instruction. It relatively requires less RAM to store instructions. It is mainly used in desktops or laptops computer.

RISC and CISC example :

Multiplying two variables X*Y:

  • CISC approach can be viewed as
    MULT X, Y
  • RISC approach can be viewed as
    LOAD R1, X
    LOAD R2, Y
    PROD X, Y
    STORE R3, X

Key Differences:

  1. RISC machine focuses more on software and less on hardware, whereas; CISC machine focuses more on hardware and less on software.
  2. RISC machine has greater use of registers so, they use transistors for more registers, whereas; CISC machine uses a greater number of complex instructions, so they use transistors to store all their complex instructions.
  3. In RISC machine, as it follows a software-based approach that is why, the code part is large, whereas; in CISC machine, as it is complex hardware driven, this makes the code part much smaller.
  4. In RISC machine, due to its great and reliable software approach, an instruction can execute in a single clock cycle, whereas; in CISC machine, due to its more hardware driven approach, an instruction lags a little bit and takes more than one clock cycle.
  5. The RISC instructions are quite handy and easy as they can fit in a single word, whereas; the CISC instructions are quite larger than a typical word.

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Construct 3 to 8 decoder with truth table and logic gates https://programmerbay.com/construct-3-to-8-decoder-with-truth-table-and-logic-gates/ https://programmerbay.com/construct-3-to-8-decoder-with-truth-table-and-logic-gates/#respond Mon, 12 Oct 2020 18:16:00 +0000 http://programmerbay.com/?p=3108

Decoder is also a Combinational circuit which transforms given inputs to a maximum number of outputs (maximum outputs equal to 2n and n are given inputs ).

In other words, a decoder can be defined as a logic circuit that receives binary input and produces output corresponding to that very binary input.

A block diagram of decoder consists of n input lines, one or more enable inputs and 2n maximum number of output lines.

To construct a decoder, we require to know the number of all possible output lines that totally depends on the given input.

So, if n represents given input lines then possible output lines would be 2n.
Decoder with three inputs would give 8 outputs (n=2,2that is 8).

In this article, we’ll be going to design 3 to 8 decoder step by step.

Here are the steps to Construct 3 to 8 Decoder

Step 1. Now we know possible outputs for 3 inputs, so construct 3 to 8 decoder, having 3 input lines, a enable input and 8 output lines.

In the below diagram, given input represented as I2Iand I, all possible outputs named as  O0, O1, O2,O3O4, O5,O6 Oand a E were represented by Enable input.

With Enable input

3 2Bto 2B8 2Bdecoder 2BFlow2code.png

Without Enable input

new




Step 2. Now, it turns to construct the truth table for 3 to 8 decoder. E input can be considered as a control input.

Mean to say, If E equals to 0 then the decoder would be considered as disabled regardless of what inputs are,  If E equals to 1 then the decoder would work as per inputs.

Truth table without E input

InputsOutputs
I2I1I0O7O6O5O4O3O2O1O0
00000000001
00100000010
01000000100
01100001000
10000010000
10100100000
11001000000
11110000000

We can represent the following output as:

O= I0‘.I1.I2
O= I0.I1.I2

O= I0‘.I1.I2
O3 = I0.I1.I2
O4 = I0.I1.I2
O5 = I0.I1.I2
O6 = I0.I1.I2
O7 = I0.I1.I2


Truth table with E input

Inputs
Outputs
EI2I1I0O7O6O5O4O3O2O1O0
0---00000000
100000000001
100100000010
101000000100
101100001000
110000010000
110100100000
111001000000
111110000000

Step 3. With the help of the above expressions derived from the table, the circuit of a 3 to 8 decoder can be implemented.

Decoder Without E

3 2Bto 2B8 2Bdecoder 2Bwithout 2Bflow3code

Explanation:

In the above diagram, there were three input lines with their respective complements using Inverters. Each and every AND gate were holding three inputs from I1Iand Iand producing 8 outputs.

Decoder with E

 

3 2Bto 2B8 2Bwith 2Benable 2Bflow2code

Explanation:

In above diagram, there were three input lines along with their complements using Inverters. Each and every AND gate were holding four inputs from E, I1Iand Iand producing 8 outputs.

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Construct 4 to 1 Multiplexer Using Logic Gates https://programmerbay.com/construct-4-to-1-multiplexer-using-logic-gates/ https://programmerbay.com/construct-4-to-1-multiplexer-using-logic-gates/#respond Thu, 01 Oct 2020 04:50:00 +0000 http://programmerbay.com/?p=3110

A multiplexer is a Combinational circuit (it is a type of circuit whose output rely on the given inputs using various logic gates ) that takes multiple inputs and delivers only a single output. It consists input data lines, selection lines and a single output.

Multiplexer

To construct a 4 to 1 multiplexer, we need to know how many selection lines we required to create a MUX?

We require  n selection lines, where 2n represents total input lines and  n represents selection lines. (In this case, 22 that gives 4 input lines and 2 selection lines).

A multiplexer is often abbreviated as MUX or many to one circuit or parallel to serial circuit.

It is a data selector that provides the mechanism to select single binary information from many input lines and passes it to output line

Advantages of Multiplexer:

  • It is less costly and reduces transmission circuit complexity
  •  It can be used to implement many combinational circuits
  • It reduces number of wires

Applications of Multiplexer:

  • It is used in communication system i.e Satellite systems, telephone networks
  • It is used to read data from memory locations in computer memory

Types of Multiplexer
There are various types of multiplexers and few are given below:

  • 2:1 MUX
  • 4:1 MUX
  • 8:1 MUX
  • 16:1 MUX
  • 32:1 MUX

In this article, we’ll be discussion 4:1 MUX.

Here are the steps to design or construct 4 to 1 Multiplexer or 4:1 MUX using Logic Gates :

1) Now, make a diagram of multiplexer with 4 input lines, 2 selection lines and 1 output. In below diagram, A0 , A1 , A2 and A3 are input data lines, S0 and S1 are Selection lines and lastly one output line named Y.

 

MULTIPLEXER 2B4 2Bcross 2B1

2) This is how a truth table for 4 to 1 MUX looks like . According to the truth table, the output of the multiplexer fully depends on selection lines (binary data , 00,01,10 & 11) and one input would be selected from all the input data lines as the output.


Truth table

   Selection Lines    Output
S0S1Output
00A0
01A1
10A2
11A3

Above  table is created as per follow :

When S0 =0 and S1=0 , then A0 would be the output.
Similarly When S0 =0 and S1=1 , then A1 would be the output.

We can represent this by an expression.
Output = S0‘.S1‘A+ S0‘.S1A1+ S0.S1‘A2 + S0.S1 A3

3) In last step, design 4 to 1 multiplexer by using 4 AND gates and a single OR gate.
4 2Bto 2B1

Explanation:

In above diagram, there were two selection lines along with their respective complements using Inverters. Each and every AND gate were holding three inputs from S1, S0 and a particular input A. lastly, outputs of all AND gates became the input for OR gate and providing a single output.

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Difference Between Selective Repeat And Go-Back-N Sliding Window Protocol https://programmerbay.com/difference-between-selective-repeat-and-go-back-n-sliding-window-protocol/ https://programmerbay.com/difference-between-selective-repeat-and-go-back-n-sliding-window-protocol/#respond Fri, 22 May 2020 09:26:38 +0000 https://www.programmerbay.com/?p=2629 Go-Back-N protocol and Selective-Repeat protocol are sliding window protocols used to deal with errors that is occurred during data transmission.

sliding window protocols
The main difference between them is, Go-Back-N protocol retransmits all the frames starting from the damaged or corrupted frame, whereas Selective Repeat protocol only retransmits frames that are damaged.

Difference between Selective Repeat and Go-Back- N sliding window protocol:

Go-Back-N Sliding Window Protocol Selective repeat Sliding Window protocol
It acts by retransmitting all the frames in the particular order after a damaged or corrupted frame is encounteredIt acts by retransmitting only those frames which are damaged or corrupted while transmission
It uses cumulative acknowledgements It uses independent acknowledgement
In this protocol, there is a great amount of wastage of the bandwidth, if there is a high error rate in the transmissionIn this protocol, there is less wastage as compared to Go-Back-N sliding window protocol in retransmission of frames
In this, there is absolutely no need for sorting the sender or the receiver sideIn this protocol, there is a need for the sorting of frames that too on the receiver side to maintain the proper sequence of frames
Sliding window size of receiver is 1. For sender, it is NSliding window size of receiver is N. For sender, it is same as receiver which is N
It is fairly less complicated than other protocolsIt is slightly more complicated solely because it uses strategies, logics, etc. which is not present in all protocols
The receiver does not store any frame that is received after encountering the damaged frame, till the damaged frame is retransmittedThe receiver stores the frames that are received after encountering the damaged frame in a buffer, till the damaged frame is resent by the sender
It is more frequently used as compared to Selective repeat Sliding WindowIt is less frequently used as compared to Go-Back-N

 

Selective Repeat sliding window protocol:

Selective repeat is one of the sliding window protocols which is essentially responsible for detecting and correcting the error caused in the data link layer.

The Selective repeat protocol basically only retransmits the damaged or lost frame.

The retransmitted frame in the selective repeat protocol is always received out of sequence.

 

Go-back-N sliding window protocol:

Go-back-N is also one of the sliding window protocols. This protocol mechanism is essentially used to control and detect the errors occurring in the data link layer.

During the data transmission between the sender and the receiver; if the acknowledgement is lost or the frame has been damaged then the sender has to resend all the frames starting from the damaged or corrupted frame.

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Difference Between TCP/IP And OSI Model in Tabular form https://programmerbay.com/difference-between-tcp-ip-and-osi-model/ https://programmerbay.com/difference-between-tcp-ip-and-osi-model/#respond Sat, 08 Feb 2020 16:57:54 +0000 https://www.programmerbay.com/?p=2528 Both TCP/IP Model and OSI Reference Model have layered architecture and also their functionality almost look similar.

The main difference between them is, OSI reference model provides clear distinction between services,interface and protocols, whereas, TCP/IP doesn’t able to differentiate between them.

Difference between TCP/IP And OSI Reference Model in Tabular form

BasisTCP/IP ModelOSI Reference Model
Full formStands for Transmission Control Protocol/Internet ProtocolOpen Systems Interconnection Reference Model
DefinitionIt defines standardised rules that enables network communication between computer as the internetIt facilitates open communication systems to communicate using Standard Protocols
Number of LayersTCP/IP model has 4 layers, namely: Application layer Transport layer Internet layer Network access layerOSI model has 7 layers, namely: Application layer Presentation layer m,Session layer, Transport layer, Network layer, Data link layer, Physical layer
Developed byTCP/IP model was developed by DoD (Department of Defence)OSI model was developed by ISO (International Standard Organisation)
Approach followHorizontal approachVertical approach
Transport layerBoth Connection-oriented and Connection-less Connection-oriented
DifferentiationDoesn't differentiate between services,interface and protocolsDifferentiates between services,interface and protocols
Upper Layer definitionApplication Layer is corresponds to Application, Presentation and Session Layer of OSI ModelIt is separately defined
ReliabilityMoreLess
Packet delivery by Transport LayerDoesn't guarantee data packet delivery Guarantees data packet delivery
UsageUse in computer networkNo longer in use
Routing protocols and standards definitionInternet LayerNetwork Layer
Stability and RestrictionsDon't have strict boundaries and is more stableStrict boundaries and is less stable

TCP/IP Model

TCP/IP model is older than OSI model and consists 4 layer initially ,later on one more layer were added.

It defines standardised rules that enables network communication between computer as the internet.

These are the layers :-

tcp ip

  • Application Layer

It corresponds to Application, Presentation and Session Layer of OSI Model. It contains all the high-level protocols. It provides various services to perform user activities ranging from file transfer to internet surfing.

It consists of HTTP, SMTP, FTP protocols and more.

  • Transport Layer

It ensures reliable transmission of data that is sent between hosts in the form of datagrams. It supports flow control and error control to make sure data is received at destination host reliably and correctly.

TCP(Transmission Control Protocol) and UDP(User Datagram Protocol) are protocols used in this layer.

  • Internet Layer

It is responsible for transmitting data packets between hosts on a network. It routes independent data packets to correct host. It uses IP(Internet Protocol), ICMP (Internet Control Message Protocol) and ARP ( Address Resolution) protocol to achieve its function.

  • Link Layer

It is a combination of the Data Link layer and Physical layer of OSI Model. It acts as an interface between transmission links and hosts. It uses a physical address to find hosts and send data.

OSI Reference Model

OSI Model stands for Open System Interconnection reference model which was developed by ISO. It facilitates open communication systems to communicate using Standard Protocols.

It is not a network architecture as it only states what a layer should do, but not describes the exact services and protocol to be used in each layer.

It follows certain principles on the basis of which it came to the decision of having 7 layers. Each and every layer has its own separate functionality.

These are the following 7 layers in OSI model :-

OSI Model

  • Application Layer

It is the only layer that communicates with users for data directly. Network applications such as Skype, Chrome and other applications work in this layer.

They use application layer protocols such as HTTP, SMTP, FTP, POP3 to function. Application layer provides various services to perform user activities ranging from file transfer to internet surfing.

  • Presentation Layer

It accepts data from the application layer in the form of a sequence of numbers or characters and transforms it into a machine-understandable form which is binary data (10101010).

After that, data compression is used to reduce the size of the data before handing it over to the next layer. It accelerates the data transmission speed and therefore, it helps in case of video calls.

Lastly, data encryption is used to encrypt data in order to maximise the integrity and security. It secures the transmitting data from intruders.

SSL protocol is one of the protocols used in this layer

Objective Highlights

    • Data Translation
    • Data Compression
    • Data Encryption
  • Session layers

It establishes, maintains, manages, and terminates connection or sessions between hosts. It uses various APIs (Application Programming Interface) to connect computers.

When a client requests for connection setup, the server uses authentication and authorisation before allowing the client to use its resources. Authentication can be defined as a process of identifying a user.

The authorisation is a process of identifying the access rights of a user, deciding what resources are allowed to access. Session layer also keeps track of which data packets belong to which file.

Objective Highlights

    • Session Establishment
    • Session Management
    • Session Termination
  • Transport Layer

It ensures communication reliability by performing segmentation, error control and flow control.

It accepts data from the session layer and divides it into various segments and each segment consists of the information of the source, destination port number and sequence number. This is known as segmentation.

Port number is used to deliver the data to correct application, whereas the sequence number is used to put the data into the correct sequence.

Further, flow control handles the amount or size of data to be transmitted. Error control comes handy when a data packets are dropped in between transmission & not reached to the destination, then using various techniques, it retransmits data again. It also uses a checksum to identify the received corrupted segment.

TCP (Transmission Control Protocol) and UDP (User Datagram Protocol) are the protocols used in this layer.

Objective Highlights

    • Data Segmentation
    • Error Control
    • Flow Control
  • Network Layer

This layer is responsible for transmitting received data segments from source host to destination host over a network.

It performs functions like logical addressing, routing and path determination. In this, each data unit is referred as data packets.

IP addressing done in this layer is called logical addressing. Each computer has an IP address to get uniquely identified on a network.

It assigns sender’s and receiver’s address to each segment, so, that they can reach at correct destination. Furthermore,
routing is also used to find an efficient and effective path from source to destination.

Lastly, path determination can be defined as a technique to select the best path for data delivery. OSPF, BGP, IS-IS are some protocols used in this layer.

Objective Highlights

    • Logical Addressing
    • Routing
    • Path Determination
  • Data Link Layer

It accepts data from the network layer. It performs physical addressing that is used to assign MAC address of sender and receiver host to received data packets to form a frame.

It also ensures the data transmission from one node to other must be error-free. It also takes care of the problem of controlling access to the shared channel using a sublayer called medium access control.

  • Physical Layer

It converts data received from the data link layer to bitstream and is responsible for actual connectivity between the devices.

It involves physical equipment ranging from cables to switches for data transfer.

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