de – Programmerbay https://programmerbay.com A Tech Bay for Tech Savvy Sun, 10 Mar 2024 16:45:29 +0000 en-US hourly 1 https://wordpress.org/?v=6.5.5 https://programmerbay.com/wp-content/uploads/2019/09/cropped-without-transparent-32x32.jpg de – Programmerbay https://programmerbay.com 32 32 Design 2 bit synchronous up down counter using T flip flop? https://programmerbay.com/design-2-bit-synchronous-up-down-counter-using-t-flip-flop/ https://programmerbay.com/design-2-bit-synchronous-up-down-counter-using-t-flip-flop/#respond Fri, 01 Mar 2024 17:29:00 +0000 http://programmerbay.com/?p=3111

These are the following steps to design 2 bit synchronous up down counter using T flip flop:

Step 1: To design a synchronous up-down counter, we need one extra input called control input. Other than this, in next state column, half of the input must be appeared as up counter and the remaining must be treated as a down counter.

Step 2: After that, we need to construct a state table with excitation table.

Note: To construct excitation table from state table you should know the excitation table of respective flip flop, in this case, it is T flip flop. So check the excitation table for T flip flop Which is:

T Flip Flop Excitation Table

Present stateNext State    T
000
011
101
110

So, the above table is the excitation table for T Flip Flop.


State Table with  excitation  table

   Control input   Present State    Next State    Flip Flop
CiQ2Q1Q'2Q'1T2T1
0000101
0011011
0101101
0110011
1001111
1010001
1100111
1111001

Above the table is created as per follow :

When Q2 =0 which is the present state and Q2‘=0 which is next state then T2 become 0 [As per excitation table, have a look ]
Similarly, if Q2 is 0 and Q2‘ is 1 then T2 becomes 1.
In a similar way, it goes on .

Step 3: After making the excitation table the next thing  to do is dig out the equation from the boolean algebra or K map for the design of the counter. So, for T1 and  T2we got 1, and Q1‘.Ci + Q1.Ci’

K-Map

 

 

For T2  Flip flop,

2 2Bbit 2Bup 2Bdown1

 

T2= Q1‘.Ci + Q1.Ci’

For TFlip flop,

2 2Bbit 2Bup 2Bdown2

 

T1=1

Step 4: Lastly according to the equation got from K map create the design for 2 bit synchronous up down counter.

 

2 2Bbit 2Bup 2Bdown

Related posts:

Design a 2 bit Synchronous down counter using T Flip flop?
Design a 2 bit Synchronous up counter using T Flip flop? 

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Design a 2 bit Synchronous down counter using T Flip flop? https://programmerbay.com/design-a-2-bit-synchronous-down-counter-using-t-flip-flop/ https://programmerbay.com/design-a-2-bit-synchronous-down-counter-using-t-flip-flop/#respond Fri, 01 Mar 2024 15:03:00 +0000 http://programmerbay.com/?p=3112

These are the following steps to design a 2 bit synchronous down counter using T Flip flop:

Step 1: To design synchronous down counter, we just require to change the order of present state and next state, just put 0 where is 1 in synchronous up counter. In other words, start from 11 (3) to 00 (0)

Step 2: After that, we need to construct a state table with excitation table.
Note: To construct excitation table from state table you should know the excitation table of respective flip flop, in this case, it is T flip flop. So check the excitation table forT flip flop Which is:

T Flip Flop Excitation Table

Present stateNext State    T
000
011
101
110

So, the above table is the excitation table for T Flip Flop.


State Table with  excitation  table

   Present State    Next State    Flip Flop
Q2Q1Q'2Q'1T2T1
001111
010001
100111
111001

Above the table is created as per follow :

When Q2 =1 which is present state and Q2‘=1 which is next state then T2 become 0 [As per excitation table, have a look ]
Similarly, if Q2 is 1and Q2‘ is 0 then T2 becomes 1.
In a similar way, it goes on.

Step 3: After making the excitation table the next thing to do is dig out the equation from the boolean algebra or K map for the design of the counter. So For T1 and T2 we got 1 and Q1‘ .

K-Map

 

For T2  Flip flop,

 

2 2BBIT 2BDown

 

 

 

T2= Q1

For TFlip flop,

Q2

 

T1=1

Step 4: Lastly according to the equation got from K map create the design for 2 bit synchronous down counter.

2 2BBIT 2BDown 2Bdesign

In above design T1 is getting high input  and T2 is getting input from the output of the T1 which is complement of the output.  A clock is attached to it which is always high in blue color.

Popular Posts:

Design a 2 bit Synchronous up counter using T Flip flop?

 

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Design 2 bit Synchronous up counter using T Flip flop? https://programmerbay.com/design-a-2-bit-synchronous-up-counter-using-t-flip-flop/ https://programmerbay.com/design-a-2-bit-synchronous-up-counter-using-t-flip-flop/#respond Thu, 29 Feb 2024 16:35:00 +0000 http://programmerbay.com/?p=3115

These are the following step to design a 2 bit Synchronous up counter using T Flip flop

Step 1: To design a synchronous up counter, first we need to know what number of flip flops are required. we can find out by considering a number of bits mentioned in the question. So, in this, we required to make 2 bit counter so the number of flip flops required is 2 [2n where n is a number of bits].

Step 2: After that, we need to construct a state table with an excitation table.

Note: To construct an excitation table from the state table you should know the excitation table of the respective flip flop, in this case, it is T flip flop. So check the excitation table forT flip flop Which is:

T Flip Flop Excitation Table

Present stateNext State    T
000
011
101
110

So, the above table is the excitation table for T Flip Flop.


State Table with  excitation  table

   Present State    Next State    Flip Flop
Q2Q1Q'2Q'1T2T1
000101
011011
101101
110011

Above the table is created as per follow :

When Q2 =0 which is the present state and Q2‘=0 which is the next state then T2 becomes 0 [As per excitation table, have a look ]
Similarly, if Q2 is 0 and Q2‘ is 1 then T2 becomes 1.
In a similar way, it goes on.

Step 3: After making the excitation table the next thing to do is dig out the equation from the boolean algebra or K map for the design of the counter. So For T1 and T2 we got 1 and Q1 .

K-Map

 

For T2  Flip flop,

k 2Bmap1
T2= Q1

For TFlip flop,

k 2Bmap2

 

T1=1

Step 4: Lastly according to the equation got from K map create the design for 2 bit synchronous up counter.

2 bit Synchronous up counter using T Flip flopIn the above design, T1 is getting high input and T2 is getting input from the output of the T1 flip flop.  A clock is attached to it which is in blue colour.

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How to Find Product Of Sums or POS from Truth Table ? https://programmerbay.com/how-to-find-product-of-sums-from-truth-table/ https://programmerbay.com/how-to-find-product-of-sums-from-truth-table/#respond Tue, 10 May 2022 08:56:00 +0000 http://programmerbay.com/?p=3098

Product Of Sum or POS Form

POS stands for Product of Sum and totally opposite to SOP form . When an expression is expressed in a product of binary terms ( A term refers to a set of binary variables, where each binary variable is combined with an operation) called Maxterms than it is said to be Product of Sum.

In other words, An expression consisting only Maxterms is called Product of Sum. For  example, (A+B)(A’+B) is a POS expression.
[other concept Minterms, A.B+A’B’]

POS can be categorized in two forms :

– Canonical or Standard POS form: In this, each and every binary variable must have in each term. For example :- (A+B).(A’+B).

– Minimal POS form: In this, the standard POS expression is reduced up in the minimum possible expression.

product 2Bof 2Bsum

A Question can be asked in three ways:-

1) In the form Truth table
2) In the form of non-canonical Expression
3) In the of form of Boolean function

 For the given table, simplify it in POS expression

Or

Find POS from Truth Table

A B Y
0 0 0 (M0)
0 1 0 (M1)
1 0 1 (M2)
1 1 1 (M3)

 

Points to Remember :

  • Always consider low output (0)
  • In Product of Sum or POS, every term in the expression is refereed to Maxterm
  • A Maxterm is represented as M(Capital M)
  • Consider A’ =1, A=0




Step 1. Since there are 2 variables , so therefore there would be 2n combinations which is 22 =4.
We consider a low output as Maxterm . a Maxterm is denoted as M.
Y= M0+M1
Y = (A+B).(A+B’)                           :- It is in Canonical POS form

In Product of Sum each term is combined with AND operation and within each term, every variable combined with OR operation.

Step 2. Now narrow the founded expression down to minimal Product of Sume or POS form. In this, you should know rules of Boolean expression or K-map

Y= A+BB’                         :-  x+yz = (x+y)(x+z)
Y= A + 0                            :- x.x’ =0
Y= A

OR

Considering, A= 0, A’=1

product 2Bof 2Bsum 2B2 2Bvariable 2B



Y= A

A is your answer.

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Construct 4 to 1 Multiplexer Using Logic Gates https://programmerbay.com/construct-4-to-1-multiplexer-using-logic-gates/ https://programmerbay.com/construct-4-to-1-multiplexer-using-logic-gates/#respond Thu, 01 Oct 2020 04:50:00 +0000 http://programmerbay.com/?p=3110

A multiplexer is a Combinational circuit (it is a type of circuit whose output rely on the given inputs using various logic gates ) that takes multiple inputs and delivers only a single output. It consists input data lines, selection lines and a single output.

Multiplexer

To construct a 4 to 1 multiplexer, we need to know how many selection lines we required to create a MUX?

We require  n selection lines, where 2n represents total input lines and  n represents selection lines. (In this case, 22 that gives 4 input lines and 2 selection lines).

A multiplexer is often abbreviated as MUX or many to one circuit or parallel to serial circuit.

It is a data selector that provides the mechanism to select single binary information from many input lines and passes it to output line

Advantages of Multiplexer:

  • It is less costly and reduces transmission circuit complexity
  •  It can be used to implement many combinational circuits
  • It reduces number of wires

Applications of Multiplexer:

  • It is used in communication system i.e Satellite systems, telephone networks
  • It is used to read data from memory locations in computer memory

Types of Multiplexer
There are various types of multiplexers and few are given below:

  • 2:1 MUX
  • 4:1 MUX
  • 8:1 MUX
  • 16:1 MUX
  • 32:1 MUX

In this article, we’ll be discussion 4:1 MUX.

Here are the steps to design or construct 4 to 1 Multiplexer or 4:1 MUX using Logic Gates :

1) Now, make a diagram of multiplexer with 4 input lines, 2 selection lines and 1 output. In below diagram, A0 , A1 , A2 and A3 are input data lines, S0 and S1 are Selection lines and lastly one output line named Y.

 

MULTIPLEXER 2B4 2Bcross 2B1

2) This is how a truth table for 4 to 1 MUX looks like . According to the truth table, the output of the multiplexer fully depends on selection lines (binary data , 00,01,10 & 11) and one input would be selected from all the input data lines as the output.


Truth table

   Selection Lines    Output
S0S1Output
00A0
01A1
10A2
11A3

Above  table is created as per follow :

When S0 =0 and S1=0 , then A0 would be the output.
Similarly When S0 =0 and S1=1 , then A1 would be the output.

We can represent this by an expression.
Output = S0‘.S1‘A+ S0‘.S1A1+ S0.S1‘A2 + S0.S1 A3

3) In last step, design 4 to 1 multiplexer by using 4 AND gates and a single OR gate.
4 2Bto 2B1

Explanation:

In above diagram, there were two selection lines along with their respective complements using Inverters. Each and every AND gate were holding three inputs from S1, S0 and a particular input A. lastly, outputs of all AND gates became the input for OR gate and providing a single output.

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Difference Between TCP/IP And OSI Model in Tabular form https://programmerbay.com/difference-between-tcp-ip-and-osi-model/ https://programmerbay.com/difference-between-tcp-ip-and-osi-model/#respond Sat, 08 Feb 2020 16:57:54 +0000 https://www.programmerbay.com/?p=2528 Both TCP/IP Model and OSI Reference Model have layered architecture and also their functionality almost look similar.

The main difference between them is, OSI reference model provides clear distinction between services,interface and protocols, whereas, TCP/IP doesn’t able to differentiate between them.

Difference between TCP/IP And OSI Reference Model in Tabular form

BasisTCP/IP ModelOSI Reference Model
Full formStands for Transmission Control Protocol/Internet ProtocolOpen Systems Interconnection Reference Model
DefinitionIt defines standardised rules that enables network communication between computer as the internetIt facilitates open communication systems to communicate using Standard Protocols
Number of LayersTCP/IP model has 4 layers, namely: Application layer Transport layer Internet layer Network access layerOSI model has 7 layers, namely: Application layer Presentation layer m,Session layer, Transport layer, Network layer, Data link layer, Physical layer
Developed byTCP/IP model was developed by DoD (Department of Defence)OSI model was developed by ISO (International Standard Organisation)
Approach followHorizontal approachVertical approach
Transport layerBoth Connection-oriented and Connection-less Connection-oriented
DifferentiationDoesn't differentiate between services,interface and protocolsDifferentiates between services,interface and protocols
Upper Layer definitionApplication Layer is corresponds to Application, Presentation and Session Layer of OSI ModelIt is separately defined
ReliabilityMoreLess
Packet delivery by Transport LayerDoesn't guarantee data packet delivery Guarantees data packet delivery
UsageUse in computer networkNo longer in use
Routing protocols and standards definitionInternet LayerNetwork Layer
Stability and RestrictionsDon't have strict boundaries and is more stableStrict boundaries and is less stable

TCP/IP Model

TCP/IP model is older than OSI model and consists 4 layer initially ,later on one more layer were added.

It defines standardised rules that enables network communication between computer as the internet.

These are the layers :-

tcp ip

  • Application Layer

It corresponds to Application, Presentation and Session Layer of OSI Model. It contains all the high-level protocols. It provides various services to perform user activities ranging from file transfer to internet surfing.

It consists of HTTP, SMTP, FTP protocols and more.

  • Transport Layer

It ensures reliable transmission of data that is sent between hosts in the form of datagrams. It supports flow control and error control to make sure data is received at destination host reliably and correctly.

TCP(Transmission Control Protocol) and UDP(User Datagram Protocol) are protocols used in this layer.

  • Internet Layer

It is responsible for transmitting data packets between hosts on a network. It routes independent data packets to correct host. It uses IP(Internet Protocol), ICMP (Internet Control Message Protocol) and ARP ( Address Resolution) protocol to achieve its function.

  • Link Layer

It is a combination of the Data Link layer and Physical layer of OSI Model. It acts as an interface between transmission links and hosts. It uses a physical address to find hosts and send data.

OSI Reference Model

OSI Model stands for Open System Interconnection reference model which was developed by ISO. It facilitates open communication systems to communicate using Standard Protocols.

It is not a network architecture as it only states what a layer should do, but not describes the exact services and protocol to be used in each layer.

It follows certain principles on the basis of which it came to the decision of having 7 layers. Each and every layer has its own separate functionality.

These are the following 7 layers in OSI model :-

OSI Model

  • Application Layer

It is the only layer that communicates with users for data directly. Network applications such as Skype, Chrome and other applications work in this layer.

They use application layer protocols such as HTTP, SMTP, FTP, POP3 to function. Application layer provides various services to perform user activities ranging from file transfer to internet surfing.

  • Presentation Layer

It accepts data from the application layer in the form of a sequence of numbers or characters and transforms it into a machine-understandable form which is binary data (10101010).

After that, data compression is used to reduce the size of the data before handing it over to the next layer. It accelerates the data transmission speed and therefore, it helps in case of video calls.

Lastly, data encryption is used to encrypt data in order to maximise the integrity and security. It secures the transmitting data from intruders.

SSL protocol is one of the protocols used in this layer

Objective Highlights

    • Data Translation
    • Data Compression
    • Data Encryption
  • Session layers

It establishes, maintains, manages, and terminates connection or sessions between hosts. It uses various APIs (Application Programming Interface) to connect computers.

When a client requests for connection setup, the server uses authentication and authorisation before allowing the client to use its resources. Authentication can be defined as a process of identifying a user.

The authorisation is a process of identifying the access rights of a user, deciding what resources are allowed to access. Session layer also keeps track of which data packets belong to which file.

Objective Highlights

    • Session Establishment
    • Session Management
    • Session Termination
  • Transport Layer

It ensures communication reliability by performing segmentation, error control and flow control.

It accepts data from the session layer and divides it into various segments and each segment consists of the information of the source, destination port number and sequence number. This is known as segmentation.

Port number is used to deliver the data to correct application, whereas the sequence number is used to put the data into the correct sequence.

Further, flow control handles the amount or size of data to be transmitted. Error control comes handy when a data packets are dropped in between transmission & not reached to the destination, then using various techniques, it retransmits data again. It also uses a checksum to identify the received corrupted segment.

TCP (Transmission Control Protocol) and UDP (User Datagram Protocol) are the protocols used in this layer.

Objective Highlights

    • Data Segmentation
    • Error Control
    • Flow Control
  • Network Layer

This layer is responsible for transmitting received data segments from source host to destination host over a network.

It performs functions like logical addressing, routing and path determination. In this, each data unit is referred as data packets.

IP addressing done in this layer is called logical addressing. Each computer has an IP address to get uniquely identified on a network.

It assigns sender’s and receiver’s address to each segment, so, that they can reach at correct destination. Furthermore,
routing is also used to find an efficient and effective path from source to destination.

Lastly, path determination can be defined as a technique to select the best path for data delivery. OSPF, BGP, IS-IS are some protocols used in this layer.

Objective Highlights

    • Logical Addressing
    • Routing
    • Path Determination
  • Data Link Layer

It accepts data from the network layer. It performs physical addressing that is used to assign MAC address of sender and receiver host to received data packets to form a frame.

It also ensures the data transmission from one node to other must be error-free. It also takes care of the problem of controlling access to the shared channel using a sublayer called medium access control.

  • Physical Layer

It converts data received from the data link layer to bitstream and is responsible for actual connectivity between the devices.

It involves physical equipment ranging from cables to switches for data transfer.

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Boolean Algebra : Simplify the following expressions using Boolean Algebra https://programmerbay.com/boolean-algebra-simplify-the-following-expressions-using-boolean-algebra/ https://programmerbay.com/boolean-algebra-simplify-the-following-expressions-using-boolean-algebra/#respond Sun, 06 May 2018 16:36:00 +0000 http://programmerbay.com/?p=3102

Simplify the following expressions using Boolean Algebra :-

 

  •  A + AB

= A.1+AB
= A(1+B)                            :-  OR (A+1 = 1)
= A.1
= A

 

  • AB+AB’

= A(B+B’)                            :- AB+AC = A(B+C)
= A(B+B’)                           :-  A + A’ =1
= A(1)
= A

  • A’BC + AC

= C(A’B+A)                         :- A+BC =  (A+B).(A+C)
= C((A’+A).(A+B))             :- A’+A=1
= C(1.(A+B))
= C(A+B)

 

  • A’B+ABC’+ABC

= A’B+AB(C’+C)                       :- A’+A=1
= A’B+AB
= B(A’+A)                                   :- A’+A=1
= B

  • A’ B’ C + A’ B C’ + A B’ C’ + A B C

 

= A’(B’C+BC’)+A(B’C’+BC)            :-  A’B+AB’ = A XOR B     , A’B+AB’ = (A XOR B)’
=A’(B XOR C) + A((B XOR C)’)      :-    let B XOR C = T ,   A’T+AT’ which implies  =A XOR T
= A XOR T                                                :-  T = B XOR C

 

=A XOR B  XOR C
 
Note: It is illustrated for beginners

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Construct 2 to 4 decoder with truth table and logic diagram https://programmerbay.com/construct-2-to-4-decoder-with-truth-table-and-logic-diagram/ https://programmerbay.com/construct-2-to-4-decoder-with-truth-table-and-logic-diagram/#respond Sun, 01 Oct 2017 16:57:00 +0000 http://programmerbay.com/?p=3109

Just as Multiplexer, Decoder is also a Combinational circuit  which transforms given inputs to maximum number of outputs(maximum outputs equal to 2n and n are given inputs ).
A block diagram of decoder consists input lines, one or more enable inputs and maximum number of output lines.
To construct a decoder, we require to know the number of all possible output lines that totally depends on the given input.
So, if  n represents given input lines then possible output lines would be 2n .
Decoder with two inputs would give 4 outputs (n=2,2that is 4).

Step 1. Now we know possible outputs for 2 inputs, so construct 2 to 4 decoder , having 2 input lines, a enable input and 4 output lines. In the below diagram, given input represented as Iand I, all possible outputs named as  O0, O1, O2, & Oand a E were represented by Enable input.

With Enable input

2 2BTO 2B1 2Bdecoder

 

Without Enable input

2 2BTO 2B1 2Bdecoder 1

Step 2. Now, it turns to construct the truth table for 2 to 4 decoder. E input can be considered as the control input. Mean to say, If E equals to 0 then the decoder would be considered as disabled regardless of what inputs are,  If E equals to 1 then the decoder would work as per inputs.

Truth table without E input

 

Inputs Outputs
I1 I0 O3 O2 O1 O0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

As per the above table, I0 would give Oand O3 and I1 would give O1 and O3.
We can represent the following output as:

O= I0‘.I1
 O= I0.I1

 O= I0‘.I1
 O3 = I0.I1


Truth table with E input

Inputs Outputs
E I1 I0 O3 O2 O1 O0
0 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Decoder with E

2 2Bto 2Bdecoder 2Bdiagram 2Bwith 2BE

 

Explanation:

In above diagram, there were two input lines along with their complements using Inverters. Each and every AND gate were holding three inputs from E, Iand Iand producing 4 outputs.

Decoder Without E

2 2Bto 2Bdecoder 2Bdiagram

Explanation:

In above diagram, there were two input lines with their respective complements using Inverters. Each and every AND gate were holding two inputs from Iand Iand producing 4 outputs.

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