Construct 3 to 8 decoder with truth table and logic gates

Sandeep Verma — Mon, 12 Oct 2020 18:16:00 +0000

Decoder is also a Combinational circuit which transforms given inputs to a maximum number of outputs (maximum outputs equal to 2ⁿ and n are given inputs ).

In other words, a decoder can be defined as a logic circuit that receives binary input and produces output corresponding to that very binary input.

A block diagram of decoder consists of n input lines, one or more enable inputs and 2ⁿmaximum number of output lines.

To construct a decoder, we require to know the number of all possible output lines that totally depends on the given input.

So, if n represents given input lines then possible output lines would be 2ⁿ.
Decoder with three inputs would give 8 outputs (n=2,2³that is 8).

In this article, we’ll be going to design 3 to 8 decoder step by step.

Here are the steps to Construct 3 to 8 Decoder

Step 1. Now we know possible outputs for 3 inputs, so construct 3 to 8 decoder, having 3 input lines, a enable input and 8 output lines.

In the below diagram, given input represented as I2, I1 and I0 , all possible outputs named as O_0,O_1,O_2,O₃_,O_4,O_5,O₆_&O₇and a E were represented by Enable input.

With Enable input

Without Enable input

Step 2. Now, it turns to construct the truth table for 3 to 8 decoder. E input can be considered as a control input.

Mean to say, If E equals to 0 then the decoder would be considered as disabled regardless of what inputs are, If E equals to 1 then the decoder would work as per inputs.

Truth table without E input

Inputs			Outputs
I₂	I₁	I₀	O₇	O₆	O₅	O₄	O₃	O₂	O₁	O₀
0	0	0	0	0	0	0	0	0	0	1
0	0	1	0	0	0	0	0	0	1	0
0	1	0	0	0	0	0	0	1	0	0
0	1	1	0	0	0	0	1	0	0	0
1	0	0	0	0	0	1	0	0	0	0
1	0	1	0	0	1	0	0	0	0	0
1	1	0	0	1	0	0	0	0	0	0
1	1	1	1	0	0	0	0	0	0	0

We can represent the following output as:

O₀= I₀‘.I₁‘.I₂‘
O₁= I₀.I₁‘.I₂‘

O₂= I₀‘.I₁.I₂‘
O₃ = I₀.I₁.I₂‘
O₄ = I₀‘.I₁‘.I₂
O₅ = I₀.I₁‘.I₂
O₆ = I₀‘.I₁.I₂
O₇ = I₀.I₁.I₂

Truth table with E input

Inputs				Outputs
E	I₂	I₁	I₀	O₇	O₆	O₅	O₄	O₃	O₂	O₁	O₀
0	-	-	-	0	0	0	0	0	0	0	0
1	0	0	0	0	0	0	0	0	0	0	1
1	0	0	1	0	0	0	0	0	0	1	0
1	0	1	0	0	0	0	0	0	1	0	0
1	0	1	1	0	0	0	0	1	0	0	0
1	1	0	0	0	0	0	1	0	0	0	0
1	1	0	1	0	0	1	0	0	0	0	0
1	1	1	0	0	1	0	0	0	0	0	0
1	1	1	1	1	0	0	0	0	0	0	0

Step 3. With the help of the above expressions derived from the table, the circuit of a 3 to 8 decoder can be implemented.

Decoder Without E

Explanation:

In the above diagram, there were three input lines with their respective complements using Inverters. Each and every AND gate were holding three inputs from I1, I1 and I0 and producing 8 outputs.

Decoder with E

Explanation:

In above diagram, there were three input lines along with their complements using Inverters. Each and every AND gate were holding four inputs from E, I1, I1 and I0 and producing 8 outputs.

Construct 4 to 1 Multiplexer Using Logic Gates

Sandeep Verma — Thu, 01 Oct 2020 04:50:00 +0000

A multiplexer is a Combinational circuit (it is a type of circuit whose output rely on the given inputs using various logic gates ) that takes multiple inputs and delivers only a single output. It consists input data lines, selection lines and a single output.

To construct a 4 to 1 multiplexer, we need to know how many selection lines we required to create a MUX?

We require n selection lines, where 2ⁿ represents total input lines and n represents selection lines. (In this case, 2² that gives 4 input lines and 2 selection lines).

A multiplexer is often abbreviated as MUX or many to one circuit or parallel to serial circuit.

It is a data selector that provides the mechanism to select single binary information from many input lines and passes it to output line

Advantages of Multiplexer:–

It is less costly and reduces transmission circuit complexity
It can be used to implement many combinational circuits
It reduces number of wires

Applications of Multiplexer:

It is used in communication system i.e Satellite systems, telephone networks
It is used to read data from memory locations in computer memory

Types of Multiplexer
There are various types of multiplexers and few are given below:

2:1 MUX
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX

In this article, we’ll be discussion 4:1 MUX.

Here are the steps to design or construct 4 to 1 Multiplexer or 4:1 MUX using Logic Gates :

1) Now, make a diagram of multiplexer with 4 input lines, 2 selection lines and 1 output. In below diagram, A₀ , A₁ , A₂ and A₃ are input data lines, S₀ and S₁ are Selection lines and lastly one output line named Y.

2) This is how a truth table for 4 to 1 MUX looks like . According to the truth table, the output of the multiplexer fully depends on selection lines (binary data , 00,01,10 & 11) and one input would be selected from all the input data lines as the output.

Truth table

Selection Lines		Output
S₀	S₁	O_utput
0	0	A₀
0	1	A₁
1	0	A₂
1	1	A₃

Above table is created as per follow :

When S₀ =0 and S₁=0 , then A₀ would be the output.
Similarly When S₀ =0 and S₁=1 , then A₁ would be the output.

We can represent this by an expression.
Output = S₀‘.S₁‘A₀+ S₀‘.S₁A₁+ S₀.S₁‘A₂ + S₀.S₁ A₃

3) In last step, design 4 to 1 multiplexer by using 4 AND gates and a single OR gate.

Explanation:

In above diagram, there were two selection lines along with their respective complements using Inverters. Each and every AND gate were holding three inputs from S₁, S₀ and a particular input A. lastly, outputs of all AND gates became the input for OR gate and providing a single output.

logic gates – Programmerbay